The present invention relates to electrical circuits of the digital-logic type, and more particularly concerns regularized integrated-circuit structures which can be personalized to perform many different logic functions. Such "programmable logic arrays" have been used to replace random logic in many fields, and are especially useful in the control section of microprogrammed data processors.
A programmable logic array (PLA) may be viewed in several different ways. Its inputs may be considered to be word addresses to a potentially very large read-only storage (ROS), and its outputs represent the contents of the addressed word; however, only a relatively small number of the potentially addressable words are actually implemented in the PLA. Another way to view a PLA is as an associative or content-addressable memory (CAM). The inputs then may be taken to represent a search argument, and the outputs represent the logic sum of all the matches for that argument. The third approach is to consider a PLA as a generalized two-level Boolean logic circuit, capable of implementing a certain number of product terms involving any of the inputs, and of OR'ing any of these terms to any output.
This third approach emphasizes the actual physical structure of the PLA. While the PLA user frequently finds it more convenient to think in terms of ROS and CAM concepts, the Boolean-logic view reminds him that the actual resources available to implement these concepts are limited to a fixed, and relatively small, number of logic functions of a particular kind. These functions are usually called "product terms", although they may not actually be simple logical products, in some implementations. In order to make most efficient use of the PLA's resources, the user must employ one of the conventional minimization techniques (e.g., Karnaugh mapping) for the overall function to be implemented. When the goal is to recognize the presence of particular input combinations, conventional PLA structures are efficient. For example, an output representing the occurrence of the specific input pattern 10011110, or of the specific group 1110XXXX (where X represents a "don't care" condition) can be performed with only a single product term each.
It is just as likely, however, that the user will desire an output to represent the absence of a particular combination, rather than its presence. He may wish, for example, to increment a counter for all input combinations except 10011110, or upon the non-occurrence of an operation code in the group 1110XXXX. Such negative conditions become very difficult to implement in conventional PLA's, because they require an excessive number of the type of product terms heretofore made available. Another frequent requirement involves the activation of an output bit upon the simultaneous occurrence of one positive and one negative condition, such as the first four inputs being all zeros, while the next four inputs are not all ones. In a microprogram control unit, for example, an instruction might require the repetition of an action for a specified number of times. The repetition condition might be most conveniently expressed as the presence of a particular operation code and a count-down register contents of other than zero. Again, conventional PLA structures implement such conditions only at an excessive cost in terms of the number of product terms which can be placed on a single chip.